 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| a FEATURES Low Power 1.7 mA/Amplifier Supply Current Fully Specified for 5 V and +5 V Supplies High Output Current, 125 mA High Speed 350 MHz, -3 dB Bandwidth (G = +1) 150 MHz, -3 dB Bandwidth (G = +2) 2,250 V/ s Slew Rate 20 ns Settling Time to 0.1% Low Distortion -72 dBc Worst Harmonic @ 500 kHz, R L = 100 -66 dBc Worst Harmonic @ 5 MHz, RL = 1 k Good Video Specifications (RL = 1 k , G = +2) 0.02% Differential Gain Error 0.06 Differential Phase Error Gain Flatness 0.1 dB to 40 MHz 60 ns Overdrive Recovery Low Offset Voltage, 1.5 mV Low Voltage Noise, 2.5 nV/Hz Available in 8-Lead SOIC and 8-Lead microSOIC APPLICATIONS XDSL, HDSL Line Driver ADC Buffer Professional Cameras CCD Imaging System Ultrasound Equipment Digital Camera PRODUCT DESCRIPTION DISTORTION - dBc OUT1 -IN1 +IN1 -VS Dual 350 MHz Low Power Amplifier AD8012* FUNCTIONAL BLOCK DIAGRAM 1 2 3 4 8 +VS 7 OUT2 6 -IN2 AD8012 5 +IN2 -40 G = +2 VOUT = 2V p-p RF = 750 -50 -60 -70 3rd -80 2nd The AD8012 is a dual low power current feedback amplifier capable of providing 350 MHz bandwidth while using only 1.7 mA per amplifier. It is intended for use in high frequency, wide dynamic range systems where low distortion, high speed are essential and low power is critical. With only 1.7 mA of supply current, the AD8012 also offers exceptional ac specs such as 20 ns settling time and 2,250 V/s slew rate. The video specifications are 0.02% differential gain and 0.06 degree differential phase, excellent for such a low power amplifier. In addition, the AD8012 has a low offset of 1.5 mV. The AD8012 is well suited for any application that requires high performance with minimal power. The product is available in standard 8-lead SOIC or microSOIC packages and operates over the industrial temperature range -40C to +85C. -90 10 100 RL - 1k Figure 1. Distortion vs. Load Resistance, VS = 5 V, Frequency = 500 kHz +VS + AMP 1 R1 + VIN VREF RL = 100 OR 135 R2 VOUT LINE POWER IN dB - - -VS Np:Ns TRANSFORMER Figure 2. Differential Drive Circuit for XDSL Applications *Protected under U.S. Patent Number 5,537,079. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999 AD8012-SPECIFICATIONS DUAL SUPPLY (@ T = +25 C, V = A S 5 V, G = +2, RL = 100 Conditions , RF = RG = 750 , unless otherwise noted) Min 270 95 Typ 350 150 90 40/23 75 2,250 3 20 35 60 Max Units MHz MHz MHz MHz MHz V/s ns ns ns ns Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth 0.1 dB Bandwidth Large Signal Bandwidth Slew Rate Rise and Fall Time Settling Time Overdrive Recovery NOISE/HARMONIC PERFORMANCE Distortion 2nd Harmonic 3rd Harmonic Output IP3 IMD Crosstalk Input Voltage Noise Input Current Noise Differential Gain Differential Phase DC PERFORMANCE Input Offset Voltage Open-Loop Transimpedance INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Bias Current Common-Mode Rejection Ratio Input Common-Mode Voltage Range OUTPUT CHARACTERISTICS Output Resistance Output Voltage Swing Output Current Short Circuit Current POWER SUPPLY Supply Current/Amp Operating Range Power Supply Rejection Ratio Specifications subject to change without notice. G = +1, VOUT < 0.4 V p-p, RL = 1 k G = +2, VOUT < 0.4 V p-p, RL = 1 k G = +2, VOUT < 0.4 V p-p, RL = 100 VOUT < 0.4 V p-p, RL = 1 k/100 VOUT = 4 V p-p VOUT = 4 V p-p VOUT = 2 V p-p 0.1%, VOUT = 2 V p-p 0.02%, VOUT = 2 V p-p 2x Overdrive VOUT = 2 V p-p, G = +2 500 kHz, RL = 1 k/100 5 MHz, RL = 1 k/100 500 kHz, RL = 1 k/100 5 MHz, RL = 1 k/100 500 kHz, f = 10 kHz, RL = 1 k/100 500 kHz, f = 10 kHz, RL = 1 k/100 5 MHz, RL = 100 f = 10 kHz f = 10 kHz, +Input, -Input f = 3.58 MHz, RL = 150 /1 k, G = +2 f = 3.58 MHz, RL = 150 /1 k, G = +2 -89/-73 -78/-62 -84/-72 -66/-52 30/40 -79/-77 -70 2.5 15 0.02/0.02 0.3/0.06 1.5 4 5 dBc dBc dBc dBc dBm dBc dB nV/Hz pA/Hz % Degrees mV mV k k k pF A A dB V V mA mA 1.8 1.9 6.0 mA mA V dB TMIN -T MAX VOUT = 2 V, RL = 100 TMIN -T MAX +Input +Input +Input, -Input +Input, -Input, TMIN -T MAX VCM = 2.5 V 240 200 500 450 2.3 3 -56 3.8 -60 4.1 0.1 4 125 500 1.7 12 15 G = +2 TMIN -T MAX 3.85 70 TMIN -T MAX Dual Supply 1.5 -58 -60 -2- REV. A AD8012 SINGLE SUPPLY (@ T +25 C, V A S = +5 V, G = +2, RL = 100 Conditions , R F = RG = 750 , unless otherwise noted) Min 220 90 Typ 300 140 85 43/24 60 1,200 2 25 40 60 Max Units MHz MHz MHz MHz MHz V/s ns ns ns ns Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth 0.1 dB Bandwidth Large Signal Bandwidth Slew Rate Rise and Fall Time Settling Time Overdrive Recovery NOISE/HARMONIC PERFORMANCE Distortion 2nd Harmonic 3rd Harmonic Output IP3 IMD Crosstalk Input Voltage Noise Input Current Noise Differential Gain Differential Phase DC PERFORMANCE Input Offset Voltage Open-Loop Transimpedance INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Bias Current Common-Mode Rejection Ratio Input Common-Mode Voltage Range OUTPUT CHARACTERISTICS Output Resistance Output Voltage Swing Output Current Short Circuit Current POWER SUPPLY Supply Current/Amp Operating Range Power Supply Rejection Ratio Specifications subject to change without notice. G = +1, VOUT < 0.4 V p-p, RL = 1 k G = +2, VOUT < 0.4 V p-p, RL = 1 k G = +2, VOUT < 0.4 V p-p, RL = 100 VOUT < 0.4 V p-p, RL = 1 k/100 VOUT = 2 V p-p VOUT = 3 V p-p VOUT = 2 V p-p 0.1%, VOUT = 2 V p-p 0.02%, VOUT = 2 V p-p 2x Overdrive VOUT = 2 V p-p, G = +2 500 kHz, RL = 1 k/100 5 MHz, RL = 1 k/100 500 kHz, RL = 1 k/100 5 MHz, RL = 1 k/100 500 kHz, RL = 1 k/100 500 kHz, RL = 1 k/100 5 MHz, RL = 100 f = 10 kHz f = 10 kHz, +Input, -Input Black Level Clamped to +2 V, f = 3.58 MHz RL = 150 /1 k RL = 150 /1 k -87/-71 -77/-61 -89/-72 -78/-52 30/40 -77/-80 -70 2.5 15 0.03/0.03 0.4/0.08 1 3 4 dBc dBc dBc dBc dBm dBc dB nV/Hz pA/Hz % Degrees mV mV k k k pF A A dB V V mA mA 1.75 1.85 12 mA mA V dB TMIN -T MAX VOUT = 2 V p-p, RL = 100 TMIN -T MAX +Input +Input +Input, -Input +Input, -Input, TMIN -T MAX VCM = 1.5 V to 3.5 V 200 150 400 450 2.3 3 -56 1.5 to 3.5 -60 1.2 to 3.8 0.1 0.9 to 4.2 100 500 1.55 12 15 G = +2 TMIN -T MAX 1 to 4 50 TMIN -T MAX Single Supply 3 -58 -60 REV. A -3- AD8012 ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V Internal Power Dissipation2 Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . 0.8 W microSOIC Package (RM) . . . . . . . . . . . . . . . . . . . . . 0.6 W Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . 2.5 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range RM, R . . . . . . -65C to +125C Operating Temperature Range (A Grade) . . -40C to +85C Lead Temperature Range (Soldering 10 sec) . . . . . . . +300C NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Specification is for device in free air at +25 C 8-Lead SOIC Package: JA = 155C/W 8-Lead microSOIC Package: JA = 200C/W The maximum power that can be safely dissipated by the AD8012 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175C for an extended period can result in device failure. The output stage of the AD8012 is designed for maximum load current capability. As a result, shorting the output to common can cause the AD8012 to source or sink 500 mA. To ensure proper operation, it is necessary to observe the maximum power derating curves. Direct connection of the output to either power supply rail can destroy the device. 2.0 MAXIMUM POWER DISSIPATION - Watts TJ = +150 C 1.5 8-LEAD SOIC PACKAGE 1.0 0.5 8-LEAD microSOIC 0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE - C 80 90 Figure 3. Plot of Maximum Power Dissipation vs. Temperature for AD8012 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8012 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 8-Lead SOIC 13" Tape and Reel 7" Tape and Reel 8-Lead microSOIC 13" Tape and Reel 7" Tape and Reel Package Options SO-8 SO-8 SO-8 RM-08 RM-08 RM-08 Brand Code Model AD8012AR AD8012AR-REEL AD8012AR-REEL7 AD8012ARM AD8012ARM-REEL AD8012ARM-REEL7 H6A H6A H6A -4- REV. A Typical Performance Characteristics- AD8012 750 750 VOUT RL VIN 49.9 0.1 F 0.1 F + + 10 F 10 F -VS VIN 53.6 +VS 0.1 F 0.1 F + + 10 F 10 F -VS RL 750 750 VOUT +VS Figure 4. Test Circuit; Gain = +2 Figure 7. Test Circuit; Gain = -1 20mV 5ns 20mV 5ns Figure 5.* 100 mV Step Response; G = +2, VS = 2.5 V or 5 V, RL = 1 k Figure 8.* 100 mV Step Response; G = -1, V S = 2.5 V or 5 V, RL = 1 k 1V 10ns 1V 10ns Figure 6. 4 V Step Response; G = +2, V S = 5 V, RL = 1 k Figure 9. 4 V Step Response; G = -1, VS = 5 V, RL = 1 k *NOTE: VS = 2.5 V operation is identical to VS = +5 V single supply operation. REV. A -5- AD8012 20mV 5ns 20mV 5ns Figure 10.* 100 mV Step Response; G = +2, VS = 2.5 V or 5 V, RL = 100 Figure 13.* 100 mV Step Response; G = -1, VS = 2.5 V or 5 V, RL = 100 500mV 10ns 500mV 10ns Figure 11. 2 V Step Response; G = +2, VS = 2.5 V, RL = 100 Figure 14. 2 V Step Response; G = -1, VS = 2.5 V, RL = 100 1V 10ns 1V 10ns Figure 12. 4 V Step Response; G = +2, VS = 5 V, RL = 100 Figure 15. 4 V Step Response; G = -1, VS = 5 V, RL = 100 *NOTE: VS = 2.5 V operation is identical to VS = +5 V single supply operation. -6- REV. A AD8012 -40 G = +2 VOUT = 2V p-p RF = 750 DISTORTION - dBc -40 G = +2 VOUT = 2V p-p RF = 750 2nd DISTORTION - dBc -60 -60 -50 -50 -70 3rd -70 3rd -80 -80 2nd -90 10 100 RL - 1k -90 10 100 RL - 1k Figure 16. Distortion vs. Load Resistance; VS = 5 V, Frequency = 500 kHz Figure 19. Distortion vs. Load Resistance; VS = +5 V, Frequency = 500 kHz -40 3rd RL = 100 2nd RL = 100 -40 3rd RL = 100 DISTORTION - dBc dBc -60 -60 2nd RL = 100 DISTORTION 3rd RL = 1k -80 2nd RL = 1k G = +2 VOUT = 2V p-p RF = 750 2nd RL = 1k -80 3rd RL = 1k -100 G = +2 VOUT = 2V p-p RF = 750 -100 1 FREQUENCY MHz 10 20 1 FREQUENCY - MHz 10 20 Figure 17. Distortion vs. Frequency; VS = 5 V Figure 20. Distortion vs. Frequency; VS = +5 V 0.5 0.4 0.3 dB 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.1 1 FREQUENCY 10 MHz 100 G = +2 VO = 0.3V p-p RF = 750 RL = 100 VS = 5V 0.5 0.4 0.3 dB 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.1 1 FREQUENCY 10 MHz 100 G = +2 VO = 0.3V p-p RF = 750 RL = 100 VS = +5V NORMALIZED GAIN Figure 18. Gain Flatness; VS = 5 V NORMALIZED GAIN Figure 21. Gain Flatness; VS = +5 V REV. A -7- AD8012 5 4 3 dB 2 1 0 -1 -2 -3 -4 -5 1 10 FREQUENCY 100 MHz 500 G = +10 G = +2 G = +1 VO = 0.3V p-p RF = 750 RL = 100 VS = 5V 5 4 3 dB 2 1 0 -1 -2 -3 -4 -5 1 10 FREQUENCY - MHz 100 500 G = +10 G = +2 G = +1 VO = 0.3V p-p RF = 750 RL = 100 VS = +5V NORMALIZED GAIN Figure 22. Frequency Response; VS = 5 V NORMALIZED GAIN Figure 25. Frequency Response; VS = +5 V 9 6 3 dBV 1V RMS 0 -3 -6 -9 -12 -15 -18 -21 1 10 FREQUENCY 100 MHz 500 G = +2 RF = 750 RL = 100 VS = 5V 3 1VRMS 0 -3 dBV -6 -9 -12 -15 -18 -21 -24 -27 1 10 FREQUENCY 100 MHz 500 G = +2 RF = 750 RL = 100 VS = +5V OUTPUT VOLTAGE Figure 23. Output Voltage vs. Frequency; V S = 5 V, G = +2 V, RL = 100 Figure 26. Output Voltage vs. Frequency; VS = +5 V, G = +2 V, RL = 100 0 -10 -20 -30 dB PSRR - dB -40 -50 -60 -70 -80 -90 -100 0.03 10 1 FREQUENCY - MHz VIN = 0.2V p-p VS = 5V, +5V OUTPUT VOLTAGE 0 -10 -20 -30 +PSRR -40 -50 -60 -70 -80 -90 0.1 100 500 -100 100k 1M 10M FREQUENCY - Hz 100M 500M VS = +5V OR G = +2 RF = 750 5V -PSRR CMRR Figure 24. CMRR vs. Frequency; V S = 5 V, +5 V Figure 27. PSRR vs. Frequency; VS = 5 V, +5 V -8- REV. A AD8012 1k 4.0 3.8 INPUT VOLTAGE NOISE - nV/ Hz 100 OUTPUT RESISTANCE G = +2 RF = 750 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 0.01 0.03 2.0 100 VOLTAGE NOISE 1k 10k FREQUENCY - Hz CURRENT NOISE +IN/-IN 30 28 26 24 22 20 18 16 14 12 10 100k INPUT CURRENT NOISE - pA/ Hz 10 VS = +5V 1 VS = 5V 0.1 0.1 10 1 FREQUENCY - MHz 100 500 Figure 28. Output Resistance vs. Frequency Figure 31. Noise vs. Frequency V 135 115 95 75 55 35 15 -5 1E+03 0 -40 -80 PHASE - Degrees -120 -160 -200 -240 -280 1E+09 9 RL = 1k 8 7 6 RL = 100 5 4 3 2 1 0 f = 5MHz G= 2 R F = 750 PHASE TZ(s) PEAK-TO-PEAK OUTPUT AT 5MHz ( 1% THD) TZ dB 1E+04 1E+05 1E+06 FREQUENCY 1E+07 Hz 1E+08 3 4 5 6 7 8 TOTAL SUPPLY VOLTAGE 9 Volts 10 11 Figure 29. Open-Loop Transimpedance and Phase vs. Frequency Figure 32. Output Swing vs. Supply 9 8 7 6 5 +5V 4 3 2 1 0 10 5V OUTPUT VOLTAGE ERROR - 0.1%/Div G = +2 RF = 750 RL = 100 2V STEP SWING - V p-p 0.1% 100 LOAD - 1k 10k 5ns t=0 Figure 30. Output Swing vs. Load Figure 33. Settling Time, VS = 5 V REV. A -9- AD8012 5 4 3 dB 2 1 0 G = +1 -1 G = +10 -2 G = +2 -3 -4 -5 1 10 FREQUENCY - MHz 100 500 VO = 0.3V p-p RF = 750 RL = 1k dB 5 4 3 2 1 0 G = +1 -1 -2 -3 -4 -5 1 10 FREQUENCY - MHz 100 500 G = +10 G = +2 VO = 0.3V p-p RF = 750 RL = 1k NORMALIZED GAIN Figure 34. Frequency Response; VS = 5 V NORMALIZED GAIN Figure 37. Frequency Response; VS = +5 V 0.5 0.4 0.3 NORMALIZED GAIN - dB 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.1 1 10 FREQUENCY - MHz 100 VO = 0.3V p-p G = +2 RF = 750 RL = 1k 0.5 0.4 0.3 NORMALIZED GAIN - dB 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.1 1 10 FREQUENCY - MHz 100 VO = 0.3V p-p RF = 750 RL = 1k Figure 35. Gain Flatness; VS = 5 V Figure 38. Gain Flatness; VS = +5 V -20 -30 INPUT REFERRED ERROR - dB -40 -50 -60 -70 -80 SIDE 2 -90 -100 -3V DRIVER VO = 2V p-p RL = 100 +3V VOUT 0V SIDE 1 VIN 0V 0V VIN 0V VOUT -110 -120 0.03 VOUT, 2V/DIV 0.1 10 1 FREQUENCY - MHz 100 500 20ns Figure 36. Crosstalk vs. Frequency Figure 39. Overdrive Recovery; VS = 5 V, G = +2, RF = 750 , RL = 100 , V IN = 3 V p-p (T = 1 s) -10- REV. A AD8012 THEORY OF OPERATION The AD8012 is a dual high speed CF amplifier that attains new levels of bandwidth (BW), power, distortion and signal swing capability. Its wide dynamic performance (including noise) is the result of both a new complementary high speed bipolar process and a new and unique architectural design. The AD8012 basically uses a two gain stage complementary design approach versus the traditional "single stage" complementary mirror structure sometimes referred to as the Nelson amplifier. Though twin stages have been tried before, they typically consumed high power since they were of a folded cascade design much like the AD9617. This design allows for the standing or quiescent current to add to the high signal or slew current-induced stages. In the time domain, the large signal output rise/fall time and slew rate is typically controlled by the small signal BW of the amplifier and the input signal step amplitude respectively, not the dc quiescent current of the gain stages (with the exception of input level shift diodes Q1/Q2). Using two stages vs. one also allows for a higher overall gain bandwidth product (GBWP) for the same power, thus lower signal distortion and the ability to drive heavier external loads. In addition, the second gain stage also isolates (divides down) A3's input reflected load drive and the nonlinearities created resulting in relatively lower distortion and higher open-loop gain. Overall, when "high" external load drive and low ac distortion is a requirement, a twin gain stage integrating amplifier like the AD8012 will provide excellent results for lower power over the traditional single stage complementary devices. In addition, being a CF amplifier, closed-loop BW variations versus external gain variations (varying RN) will be much lower compared to a VF op amp, where the BW varies inversely with gain. Another key attribute of this amplifier is its ability to run on a single 5 V supply due in part to its wide common-mode input and output voltage range capability. For 5 V supply operation, the device obviously consumes half the quiescent power (vs. 10 V supply) with little degradation in its ac and dc performance characteristics. See data sheet comparisons. DC GAIN CHARACTERISTICS Gain stages A1/A1B and A2/A2B combined provide negative feedforward transresistance gain. See Figure 40. Stage A3 is a unity gain buffer which provides external load isolation to A2. Each stage uses a symmetrical complementary design. (A3 is also complementary though not explicitly shown). This is done to reduce both second order signal distortion and overall quiescent power as discussed above. In the quasi dc to low frequency region, the closed loop gain relationship can be approximated as: G = 1+R F /RN G = -R F /RN noninverting operation inverting operation These basic relationships above are common to all traditional operational amplifiers. A1 IPP IPN -VI Z1 = R1 || C1 Z1 CD A2 C P1 CP2 ICQ + IO IQ1 Q3 IR + IFC Q1 VP + Q2 IE VN - ZI Z2 VO A3 RL RF RN CL VO Q4 IQ1 IR - IFC Z1 A2 C P1 CD ICQ - IO -VI INP IPN A1 AD8012 Figure 40. Simplified Block Diagram REV. A -11- AD8012 APPLICATIONS Line Driving for HDSL TO RECEIVER CIRCUITRY High Bitrate Digital Subscriber Line (HDSL) is becoming popular as a means of providing full duplex data communication at rates up to 1.544 MBPS or 2.048 MBPS over moderate distances via conventional telephone twisted pair wires. Traditional T1 (E1 in Europe) requires repeaters every 3,000 feet to 6,000 feet to boost the signal strength and allow transmission over distances of up to 12,000 feet. In order to achieve repeaterless transmission over this distance, an HDSL modem requires transmitted power level of +13.5 dBm (assuming a line impedance of 135 ). HDSL uses the Two Binary/One Quaternary line code (2B1Q). A sample 2B1Q waveform is shown in Figure 41. The digital bit stream is broken up into groups of two bits. Four analogue voltages (called quaternary symbols) are used to represent the four possible combinations of two bits. These symbols are assigned arbitrary names +3, +1, -1 and -3. The corresponding voltage levels are produced by a DAC that is usually part of an Analog Front End Circuit (AFEC). Before being applied to the line, the DAC output is low-pass filtered and acquires the sinusoidal form shown in Figure 41. Finally, the filtered signal is applied to the line driver. The line voltages that correspond to the quaternary symbols +3, +1, -1 and -3 are 2.64 V, 0.88 V, -0.88 V and -2.64 V. This gives a peak-to-peak line voltage of 5.28 V. SYMBOL NAME VOLTAGE +3 2.64V FILTERED OUTPUT TO LINE DRIVER DAC OUTPUT +5V + 1/2 AD8012 0.1 F UP TO 12,000 FEET 66.5 RF 750 6V p-p RG 1.5k RF 750 12V p-p 6V p-p 135 66.5 - 0.1 F 1:1 1:1 1/2 AD8012 TO RECEIVER CIRCUITRY -5V GAIN = +2 Figure 42. Differential for HDSL Applications The immediate effect of back-termination is that the signal from the amplifier is halved before being applied to the line. This doubles the power the amplifier must deliver. However, the back-termination resistors also play an important second role. Full-duplex data transmission systems like HDSL simultaneously transmit data in both directions. As a result, the signal on the line and across the back termination resistors is the composite of the transmitted and received signal. The termination resistors are used to tap off this signal and feed it to the receive circuitry. Because the receive circuitry "knows" what is being transmitted, the transmitted data can be subtracted from the digitized composite signal to reveal the received data. Driving a line with a differential signal offers a number of advantages compared to a single-ended drive. Because the two outputs are always 180 degrees out of phase relative to one another, the differential signal output is double the output amplitude of either of the op amps. As a result, the differential amplifier can have a peak-to-peak swing of 16 V (each op amp can swing to 4 V), even though the power supply is 5 V. +1 0.88V -1 -0.88V -3 -2.64V -1 01 +3 10 +1 11 -3 00 -3 00 +1 11 +3 10 -3 00 -1 01 -1 01 +1 11 -1 01 -3 00 Figure 41. Time Domain Representation of a HDSL Signal Many of the elements of a classic differential line driver are shown in the HDSL line driver in Figure 42. A 6 V peak-topeak differential signal is applied to the input. The differential gain of the amplifier (1+2 RF/RG) is set to +2, so the resulting differential output signal is 12 V p-p. As is normal in telephony applications, a transformer galvanically isolates the differential amplifier from the line. In this case a 1:1 turns ratio is used. In order to correctly terminate the line, it is necessary to set the output impedance of the amplifier to be equal to the impedance of the line being driven (135 in this case). Because the transformer has a turns ratio of 1:1, the impedance reflected from the line is equal to the line impedance of 135 (RREFL = R LINE/Turns Ratio2). As a result, two 66.5 resistors correctly terminate the line. In addition to this, even-order harmonics (2nd, 4th, 6th, etc.) of the two single-ended outputs tend to cancel out one another, so the Total Harmonic Distortion (quadratic sum of all harmonics) decreases compared to the single-ended case, even as the signal amplitude is doubled. This is particularly advantageous for the case of the second harmonic. As it is very close to the fundamental, filtering becomes difficult. In this application, the THD is dominated by the third harmonic which is 65 dB below the carrier (i.e., Spurious Free Dynamic Range = -65 dBc). Differential line driving also helps to preserve the integrity of the transmitted signal in the presence of Electro-Magnetic Interference (EMI). EMI tends to induce itself equally on to both the positive and negative signal line. As a result, a receiver with good common-mode rejection, will amplify the original signal while rejecting induced (common-mode) EMI. -12- REV. A AD8012 Choosing the Appropriate Turns Ratio for the Transformer Increasing the peak-to-peak output signal from the amplifier in the previous example, combined with a variation in the turns ratio of the transformer, can yield further enhancements to the circuit. The output signal swing of the AD8012 can be increased to about 3.9 V before clipping occurs. This increases the peakto-peak output of the differential amplifier to 15.6 V. Because the signal applied to the primary winding is now bigger, the transformer turns ratio of 1:1 can be replaced with a (stepdown) turns ratio of about 1.3:1 (from amplifier to line). This steps the 7.8 V peak-to-peak primary voltage down to 6 V. This is the same secondary voltage as before so the resulting power delivered to the line is the same. The received signal, which is small relative to the transmitted signal, will, however be stepped up by a factor of 1.3. Amplifying the received signal in this manner enhances its signal-to-noise ratio and is useful when the received signal is small compared to the to-be-transmitted signal. The impedance reflected from the 135 line now becomes 228 (1.3 2 times 135 ). With a correctly terminated line, the amplifier must now drive a total load of 456 (114 + 114 + 228 ), considerably less than the original 270 load. This reduces the drive current from the op amps by about 40%. More significant however is the reduction in dynamic power consumption; that is, the power the amplifier must consume in order to deliver the load power. Increasing the output signal so that it is as close as possible to the power rails, minimizes the power consumed in the amplifier. There is, however, a price to pay in terms of increased signal distortion. Increasing the output signal of each op amp from the original 3 V to 3.9 V reduces the Spurious Free Dynamic Range (SFDR) from -65 dB to -50 dB (measured at 500 kHz), even though the overall load impedance has increased from 270 to 456 . LAYOUT CONSIDERATIONS The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. The ground plane should be removed from the area near the input pins to reduce stray capacitance. Chip capacitors should be used for supply bypassing (see Figure 43). One end should be connected to the ground plane and the other within 1/8 in. of each power pin. An additional (4.7 F-10 F) tantalum electrolytic capacitor should be connected in parallel. The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance greater than 1.5 pF at the inverting input will significantly affect high speed performance when operating at low noninverting gains. Stripline design techniques should be used for long signal traces (greater than about 1 in.). These should be designed with the proper system characteristic impedance and be properly terminated at each end. RG VIN RT +VS 10 F + 0.1 F RF RO* VOUT *RO CHOSEN FOR CHARACTERISTIC IMPEDANCE. INVERTING CONFIGURATION RG RF RO* VOUT VIN RT The specified high speed performance of the AD8012 requires careful attention to board layout and component selection. Table I shows recommended component values for the AD8012 and Figures 44-49 show recommended layouts for the 8-lead SOIC and microSOIC packages for a positive gain. Proper RF design techniques and low parasitic component selections are mandatory. 0.1 F 10 F + -VS *RO CHOSEN FOR CHARACTERISTIC IMPEDANCE. NONINVERTING CONFIGURATION Figure 43. Inverting and Noninverting Configurations Table I. Typical Bandwidth vs. Gain Setting Resistors Gain -1 +1 +2 +10 RF 750 750 750 750 RG 750 - 750 82.5 RT 53.6 49.9 49.9 49.9 Small Signal -3 dB BW (MHz), VS = 5 V, RL = 1 k 110 350 150 40 RT chosen for 50 characteristic input impedance. REV. A -13- AD8012 Figure 44. Universal SOIC Noninverter Top Silkscreen Figure 47. Universal microSOIC Noninverter Top Silkscreen Figure 45. Universal SOIC Noninverter Top Figure 48. Universal microSOIC Noninverter Top Figure 46. Universal SOIC Noninverter Bottom Figure 49. Universal microSOIC Noninverter Bottom -14- REV. A AD8012 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead SOIC (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 1 5 4 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) x 45 0.0099 (0.25) SEATING PLANE 0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC 0.0098 (0.25) 0.0075 (0.19) 8 0 0.0500 (1.27) 0.0160 (0.41) 8-Lead microSOIC (RM-08) 0.122 (3.10) 0.114 (2.90) 8 5 0.122 (3.10) 0.114 (2.90) 1 4 0.199 (5.05) 0.187 (4.75) PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 33 27 0.028 (0.71) 0.016 (0.41) 0.120 (3.05) 0.112 (2.84) REV. A -15- PRINTED IN U.S.A. C3207a-0-12/99 |
Price & Availability of AD8012
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |